A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation
We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the schem...
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Zusammenfassung: | We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provides more cacheability than the previous compiler-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed. |
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DOI: | 10.1109/ISCA.1992.753340 |