A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation

We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the schem...

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Hauptverfasser:	Louri, A., Hongki Sung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Coherence Computer science Delay Engineering management Flow graphs Registers Runtime
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creator	Louri, A. Hongki Sung
description	We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provides more cacheability than the previous compiler-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.
doi_str_mv	10.1109/ISCA.1992.753340
format	Conference Proceeding
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A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.</description><subject>Application software</subject><subject>Coherence</subject><subject>Computer science</subject><subject>Delay</subject><subject>Engineering management</subject><subject>Flow graphs</subject><subject>Registers</subject><subject>Runtime</subject><isbn>0897915097</isbn><isbn>9780897915090</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9j0FLw0AUhBdEsGrv0tP7A427pjHuscQWe6gI8V4em1fyZJMNb1drD_73Btqzcxnmm7mMUg9GZ8Zo-7ipq2VmrH3KyiLPF_pK3eoXW1pTaFveqGmMX3rUojD2uZiovyW80wGq0A3sSeavLOQSNVCha2nkLQn1jqAeY0ewDwJ1izIuttQFOcL22yceJDiKMUiEA6cW1hgTYN_ABwp6Tx5Wv4Nnxwk2_Q96bjBx6O_V9R59pOnF79Rsvfqs3uZMRLtBuEM57s5H8n_LEz1QTjw</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Louri, A.</creator><creator>Hongki Sung</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1992</creationdate><title>A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation</title><author>Louri, A. ; Hongki Sung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7533403</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Application software</topic><topic>Coherence</topic><topic>Computer science</topic><topic>Delay</topic><topic>Engineering management</topic><topic>Flow graphs</topic><topic>Registers</topic><topic>Runtime</topic><toplevel>online_resources</toplevel><creatorcontrib>Louri, A.</creatorcontrib><creatorcontrib>Hongki Sung</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Louri, A.</au><au>Hongki Sung</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation</atitle><btitle>[1992] Proceedings the 19th Annual International Symposium on Computer Architecture</btitle><stitle>ISCA</stitle><date>1992</date><risdate>1992</risdate><spage>428</spage><epage>428</epage><pages>428-428</pages><isbn>0897915097</isbn><isbn>9780897915090</isbn><abstract>We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provides more cacheability than the previous compiler-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.</abstract><pub>IEEE</pub><doi>10.1109/ISCA.1992.753340</doi></addata></record>
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identifier	ISBN: 0897915097
ispartof	[1992] Proceedings the 19th Annual International Symposium on Computer Architecture, 1992, p.428-428
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subjects	Application software Coherence Computer science Delay Engineering management Flow graphs Registers Runtime
title	A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation
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