Analysis of fault transients and breakdown conditions in laminated printed circuit card structures

Analysis of fault transients and breakdown conditions in laminated printed circuit card structures

In certain embedded applications operating in harsh environments severe overvoltage conditions produced by external transients can occur. The advent and incorporation of advanced interconnect technologies and geometries worsen the problem, to the point of invalidating certain assumptions critical to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Jorgenson, J.A., Vakil, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit faults
Circuit testing
Dielectrics
Electric breakdown
Electronic packaging thermal management
Electronics packaging
Geometry
Integrated circuit interconnections
Printed circuits
Transient analysis
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Beschreibung
Zusammenfassung:In certain embedded applications operating in harsh environments severe overvoltage conditions produced by external transients can occur. The advent and incorporation of advanced interconnect technologies and geometries worsen the problem, to the point of invalidating certain assumptions critical to system survival. The purpose of this research is to determine the limits of operation, and to develop a means for analysis and prediction of reliable operation.
DOI:10.1109/ISEMC.1998.750349