Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package
Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing...
Gespeichert in:
| Veröffentlicht in: | IEEE design and test 2017-06, Vol.34 (3), p.50-58 |
|---|---|
| Hauptverfasser: | , , , , , , , |
| Format: | Magazinearticle |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 58 |
|---|---|
| container_issue | 3 |
| container_start_page | 50 |
| container_title | IEEE design and test |
| container_volume | 34 |
| creator | Kai-Li Wang Bing-Yang Lin Cheng-Wen Wu Mincent Lee Hao Chen Hung-Chih Lin Ching-Nen Peng Min-Jer Wang |
| description | Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure. |
| doi_str_mv | 10.1109/MDAT.2016.2562060 |
| format | Magazinearticle |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_7464303</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7464303</ieee_id><sourcerecordid>1897024812</sourcerecordid><originalsourceid>FETCH-LOGICAL-i203t-4054d60bbede3d680dff84b7a9086da2455a739f26f8d797e8bfaf287b4ca6163</originalsourceid><addsrcrecordid>eNo9Ts1Kw0AYXETBUvsA4mXBc-L-5dvNsURbCy0VrXgMm-y3bWrsxiQV-vYGKs5hZg7DzBByy1nMOUsfVo_TTSwYh1gkIBiwCzISHEwkJKjLf5_ANZl03Z4NMIngxozIfINdT7Mw0Cu6Y9lX4UBX2O-CC3XYnqgPLV0cZmv6YT220RJ_sKbZrmqit9LWSF9s-Wm3eEOuvK07nPzpmLzPnjbZc7RczxfZdBlVgsk-UixRDlhRoEPpwDDnvVGFtikz4KxQSWK1TL0Ab5xONZrCWy-MLlRpgYMck_tzb9OG7-PwPd-HY3sYJnNuUs2EMlwMqbtzqkLEvGmrL9uecq1ASSblL2p3Vq0</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>magazinearticle</recordtype><pqid>1897024812</pqid></control><display><type>magazinearticle</type><title>Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package</title><source>IEEE Electronic Library Online</source><creator>Kai-Li Wang ; Bing-Yang Lin ; Cheng-Wen Wu ; Mincent Lee ; Hao Chen ; Hung-Chih Lin ; Ching-Nen Peng ; Min-Jer Wang</creator><creatorcontrib>Kai-Li Wang ; Bing-Yang Lin ; Cheng-Wen Wu ; Mincent Lee ; Hao Chen ; Hung-Chih Lin ; Ching-Nen Peng ; Min-Jer Wang</creatorcontrib><description>Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure.</description><identifier>ISSN: 2168-2356</identifier><identifier>EISSN: 2168-2364</identifier><identifier>DOI: 10.1109/MDAT.2016.2562060</identifier><identifier>CODEN: IDTCEC</identifier><language>eng</language><publisher>Piscataway: IEEE Computer Society</publisher><subject>3D IC ; Analytical models ; Chip-scale packaging ; Contact resistance ; Cost analysis ; cost model ; Electronic packaging ; Electronics industry ; InFO WLCSP ; Integrated circuit modeling ; Manufacturing ; test cost analysis ; Test procedures ; Three-dimensional displays ; wafer probe ; wafer test</subject><ispartof>IEEE design and test, 2017-06, Vol.34 (3), p.50-58</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7464303$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>776,780,792,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7464303$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kai-Li Wang</creatorcontrib><creatorcontrib>Bing-Yang Lin</creatorcontrib><creatorcontrib>Cheng-Wen Wu</creatorcontrib><creatorcontrib>Mincent Lee</creatorcontrib><creatorcontrib>Hao Chen</creatorcontrib><creatorcontrib>Hung-Chih Lin</creatorcontrib><creatorcontrib>Ching-Nen Peng</creatorcontrib><creatorcontrib>Min-Jer Wang</creatorcontrib><title>Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package</title><title>IEEE design and test</title><addtitle>DTM</addtitle><description>Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure.</description><subject>3D IC</subject><subject>Analytical models</subject><subject>Chip-scale packaging</subject><subject>Contact resistance</subject><subject>Cost analysis</subject><subject>cost model</subject><subject>Electronic packaging</subject><subject>Electronics industry</subject><subject>InFO WLCSP</subject><subject>Integrated circuit modeling</subject><subject>Manufacturing</subject><subject>test cost analysis</subject><subject>Test procedures</subject><subject>Three-dimensional displays</subject><subject>wafer probe</subject><subject>wafer test</subject><issn>2168-2356</issn><issn>2168-2364</issn><fulltext>true</fulltext><rsrctype>magazinearticle</rsrctype><creationdate>2017</creationdate><recordtype>magazinearticle</recordtype><sourceid>RIE</sourceid><recordid>eNo9Ts1Kw0AYXETBUvsA4mXBc-L-5dvNsURbCy0VrXgMm-y3bWrsxiQV-vYGKs5hZg7DzBByy1nMOUsfVo_TTSwYh1gkIBiwCzISHEwkJKjLf5_ANZl03Z4NMIngxozIfINdT7Mw0Cu6Y9lX4UBX2O-CC3XYnqgPLV0cZmv6YT220RJ_sKbZrmqit9LWSF9s-Wm3eEOuvK07nPzpmLzPnjbZc7RczxfZdBlVgsk-UixRDlhRoEPpwDDnvVGFtikz4KxQSWK1TL0Ab5xONZrCWy-MLlRpgYMck_tzb9OG7-PwPd-HY3sYJnNuUs2EMlwMqbtzqkLEvGmrL9uecq1ASSblL2p3Vq0</recordid><startdate>20170601</startdate><enddate>20170601</enddate><creator>Kai-Li Wang</creator><creator>Bing-Yang Lin</creator><creator>Cheng-Wen Wu</creator><creator>Mincent Lee</creator><creator>Hao Chen</creator><creator>Hung-Chih Lin</creator><creator>Ching-Nen Peng</creator><creator>Min-Jer Wang</creator><general>IEEE Computer Society</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope></search><sort><creationdate>20170601</creationdate><title>Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package</title><author>Kai-Li Wang ; Bing-Yang Lin ; Cheng-Wen Wu ; Mincent Lee ; Hao Chen ; Hung-Chih Lin ; Ching-Nen Peng ; Min-Jer Wang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-4054d60bbede3d680dff84b7a9086da2455a739f26f8d797e8bfaf287b4ca6163</frbrgroupid><rsrctype>magazinearticle</rsrctype><prefilter>magazinearticle</prefilter><language>eng</language><creationdate>2017</creationdate><topic>3D IC</topic><topic>Analytical models</topic><topic>Chip-scale packaging</topic><topic>Contact resistance</topic><topic>Cost analysis</topic><topic>cost model</topic><topic>Electronic packaging</topic><topic>Electronics industry</topic><topic>InFO WLCSP</topic><topic>Integrated circuit modeling</topic><topic>Manufacturing</topic><topic>test cost analysis</topic><topic>Test procedures</topic><topic>Three-dimensional displays</topic><topic>wafer probe</topic><topic>wafer test</topic><toplevel>online_resources</toplevel><creatorcontrib>Kai-Li Wang</creatorcontrib><creatorcontrib>Bing-Yang Lin</creatorcontrib><creatorcontrib>Cheng-Wen Wu</creatorcontrib><creatorcontrib>Mincent Lee</creatorcontrib><creatorcontrib>Hao Chen</creatorcontrib><creatorcontrib>Hung-Chih Lin</creatorcontrib><creatorcontrib>Ching-Nen Peng</creatorcontrib><creatorcontrib>Min-Jer Wang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library Online</collection><jtitle>IEEE design and test</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kai-Li Wang</au><au>Bing-Yang Lin</au><au>Cheng-Wen Wu</au><au>Mincent Lee</au><au>Hao Chen</au><au>Hung-Chih Lin</au><au>Ching-Nen Peng</au><au>Min-Jer Wang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package</atitle><jtitle>IEEE design and test</jtitle><stitle>DTM</stitle><date>2017-06-01</date><risdate>2017</risdate><volume>34</volume><issue>3</issue><spage>50</spage><epage>58</epage><pages>50-58</pages><issn>2168-2356</issn><eissn>2168-2364</eissn><coden>IDTCEC</coden><abstract>Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure.</abstract><cop>Piscataway</cop><pub>IEEE Computer Society</pub><doi>10.1109/MDAT.2016.2562060</doi><tpages>9</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2168-2356 |
| ispartof | IEEE design and test, 2017-06, Vol.34 (3), p.50-58 |
| issn | 2168-2356 2168-2364 |
| language | eng |
| recordid | cdi_ieee_primary_7464303 |
| source | IEEE Electronic Library Online |
| subjects | 3D IC Analytical models Chip-scale packaging Contact resistance Cost analysis cost model Electronic packaging Electronics industry InFO WLCSP Integrated circuit modeling Manufacturing test cost analysis Test procedures Three-dimensional displays wafer probe wafer test |
| title | Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T20%3A54%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Test%20Cost%20Reduction%20Methodology%20for%20InFO%20Wafer-Level%20Chip-Scale%20Package&rft.jtitle=IEEE%20design%20and%20test&rft.au=Kai-Li%20Wang&rft.date=2017-06-01&rft.volume=34&rft.issue=3&rft.spage=50&rft.epage=58&rft.pages=50-58&rft.issn=2168-2356&rft.eissn=2168-2364&rft.coden=IDTCEC&rft_id=info:doi/10.1109/MDAT.2016.2562060&rft_dat=%3Cproquest_RIE%3E1897024812%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1897024812&rft_id=info:pmid/&rft_ieee_id=7464303&rfr_iscdi=true |