Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing...

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Veröffentlicht in:IEEE design and test 2017-06, Vol.34 (3), p.50-58
Hauptverfasser: Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Format: Magazinearticle
Sprache:eng
Schlagworte:
3D IC
Analytical models
Chip-scale packaging
Contact resistance
Cost analysis
cost model
Electronic packaging
Electronics industry
InFO WLCSP
Integrated circuit modeling
Manufacturing
test cost analysis
Test procedures
Three-dimensional displays
wafer probe
wafer test
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Beschreibung
Zusammenfassung:Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure.
ISSN:2168-2356
2168-2364
DOI:10.1109/MDAT.2016.2562060