Easily testable realization based on OR-AND-EXOR expansion with single rail inputs
It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 374 |
|---|---|
| container_issue | |
| container_start_page | 371 |
| container_title | |
| container_volume | |
| creator | Hirayama, T. Koda, G. Nishitani, Y. Shimizu, K. |
| description | It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1/spl les/r/spl les/n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network. |
| doi_str_mv | 10.1109/APCCAS.1998.743779 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_743779</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>743779</ieee_id><sourcerecordid>743779</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-5e78d64e3639def268afc133dbfdb5202e96bcdf277ba30e382c18f60d689dc93</originalsourceid><addsrcrecordid>eNotj9tKxDAYhAMiqOu-wF7lBVqT_m0Ol6XWAyxW6l54tyTNX43UWpqIrk-_u6xzMwMfMzCErDhLOWf6pnyuqvIl5VqrVOYgpT4jV0wqBgXPBbsgyxA-2EGgQYK6JG1tgh92NGKIxg5IZzSD_zPRf43UmoCOHkLTJuXTbVK_Ni3F38mM4Yh_fHynwY9vx5rxA_Xj9B3DNTnvzRBw-e8LsrmrN9VDsm7uH6tynXglY1KgVE7kCAK0wz4TyvQdB3C2d7bIWIZa2M71mZTWAENQWcdVL5gTSrtOw4KsTrMeEbfT7D_NvNueTsMemRROOQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Easily testable realization based on OR-AND-EXOR expansion with single rail inputs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Hirayama, T. ; Koda, G. ; Nishitani, Y. ; Shimizu, K.</creator><creatorcontrib>Hirayama, T. ; Koda, G. ; Nishitani, Y. ; Shimizu, K.</creatorcontrib><description>It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1/spl les/r/spl les/n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network.</description><identifier>ISBN: 0780351460</identifier><identifier>ISBN: 9780780351462</identifier><identifier>DOI: 10.1109/APCCAS.1998.743779</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit faults ; Circuit testing ; Computer science ; Electrical fault detection ; Electronic mail ; Equations ; Fault detection ; Input variables ; Logic testing ; Rails</subject><ispartof>IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242), 1998, p.371-374</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/743779$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/743779$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hirayama, T.</creatorcontrib><creatorcontrib>Koda, G.</creatorcontrib><creatorcontrib>Nishitani, Y.</creatorcontrib><creatorcontrib>Shimizu, K.</creatorcontrib><title>Easily testable realization based on OR-AND-EXOR expansion with single rail inputs</title><title>IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242)</title><addtitle>APCCAS</addtitle><description>It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1/spl les/r/spl les/n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Computer science</subject><subject>Electrical fault detection</subject><subject>Electronic mail</subject><subject>Equations</subject><subject>Fault detection</subject><subject>Input variables</subject><subject>Logic testing</subject><subject>Rails</subject><isbn>0780351460</isbn><isbn>9780780351462</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1998</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj9tKxDAYhAMiqOu-wF7lBVqT_m0Ol6XWAyxW6l54tyTNX43UWpqIrk-_u6xzMwMfMzCErDhLOWf6pnyuqvIl5VqrVOYgpT4jV0wqBgXPBbsgyxA-2EGgQYK6JG1tgh92NGKIxg5IZzSD_zPRf43UmoCOHkLTJuXTbVK_Ni3F38mM4Yh_fHynwY9vx5rxA_Xj9B3DNTnvzRBw-e8LsrmrN9VDsm7uH6tynXglY1KgVE7kCAK0wz4TyvQdB3C2d7bIWIZa2M71mZTWAENQWcdVL5gTSrtOw4KsTrMeEbfT7D_NvNueTsMemRROOQ</recordid><startdate>1998</startdate><enddate>1998</enddate><creator>Hirayama, T.</creator><creator>Koda, G.</creator><creator>Nishitani, Y.</creator><creator>Shimizu, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1998</creationdate><title>Easily testable realization based on OR-AND-EXOR expansion with single rail inputs</title><author>Hirayama, T. ; Koda, G. ; Nishitani, Y. ; Shimizu, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-5e78d64e3639def268afc133dbfdb5202e96bcdf277ba30e382c18f60d689dc93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Computer science</topic><topic>Electrical fault detection</topic><topic>Electronic mail</topic><topic>Equations</topic><topic>Fault detection</topic><topic>Input variables</topic><topic>Logic testing</topic><topic>Rails</topic><toplevel>online_resources</toplevel><creatorcontrib>Hirayama, T.</creatorcontrib><creatorcontrib>Koda, G.</creatorcontrib><creatorcontrib>Nishitani, Y.</creatorcontrib><creatorcontrib>Shimizu, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hirayama, T.</au><au>Koda, G.</au><au>Nishitani, Y.</au><au>Shimizu, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Easily testable realization based on OR-AND-EXOR expansion with single rail inputs</atitle><btitle>IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242)</btitle><stitle>APCCAS</stitle><date>1998</date><risdate>1998</risdate><spage>371</spage><epage>374</epage><pages>371-374</pages><isbn>0780351460</isbn><isbn>9780780351462</isbn><abstract>It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1/spl les/r/spl les/n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.1998.743779</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0780351460 |
| ispartof | IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242), 1998, p.371-374 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_743779 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit faults Circuit testing Computer science Electrical fault detection Electronic mail Equations Fault detection Input variables Logic testing Rails |
| title | Easily testable realization based on OR-AND-EXOR expansion with single rail inputs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T03%3A31%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Easily%20testable%20realization%20based%20on%20OR-AND-EXOR%20expansion%20with%20single%20rail%20inputs&rft.btitle=IEEE.%20APCCAS%201998.%201998%20IEEE%20Asia-Pacific%20Conference%20on%20Circuits%20and%20Systems.%20Microelectronics%20and%20Integrating%20Systems.%20Proceedings%20(Cat.%20No.98EX242)&rft.au=Hirayama,%20T.&rft.date=1998&rft.spage=371&rft.epage=374&rft.pages=371-374&rft.isbn=0780351460&rft.isbn_list=9780780351462&rft_id=info:doi/10.1109/APCCAS.1998.743779&rft_dat=%3Cieee_6IE%3E743779%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=743779&rfr_iscdi=true |