Robust Soft Error Tolerant CMOS Latch Configurations

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performan...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on computers 2016-09, Vol.65 (9), p.2820-2834
Hauptverfasser:	Anjan Kumar, Pudi N. S., Baghini, Maryam Shojaei
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit faults Circuits Clocks CMOS Computer simulation Delay Delays Faults Feedback loop hardened latch Impedance Latches Soft error Soft errors Specifications static latch Transient analysis transient fault
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!