Robust Soft Error Tolerant CMOS Latch Configurations

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed configurations provide a more relaxed tradeoff between SER and other specifications mainly delay, power dissipation and area. RTL implementation of a proposed latch is also shown to verify the behaviour subjected to the transient faults. The benefit of implementing a SE tolerant circuit in VHDL language is the feasibility to exhaustively check the immunity of the circuit against transient faults at every sensitive node by just writing simple boolean expressions of each element in the circuit. The proposed configurations and a few selected reported configurations have been also designed, laid out and post layout extracted in 90 nm CMOS logic technology. Post layout simulations have been performed on all proposed latch configurations with clock frequency of 500 MHz and performance comparison results are presented.