Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology

This brief presents the analysis and design of a two-stage stacked power amplifier (PA) with very broadband gain frequency response and power performance in a small chip size. The broadband load impedance match is realized using modified stacked field-effect transistors (FETs) with a resistive feedback by analyzing the matching condition of the source input impedance of the stacked FET. In order to further improve the broadband gain frequency response, the effectiveness of a gain expansion from a stacked driver amplifier is demonstrated to compensate the gain compression of the last-stage amplifier. To verify the design concept, a two-stage three-stacked PA has been implemented in a 0.18-μm CMOS technology. The PA achieves a saturated output power of 22-24.3 dBm and a power added efficiency of 13%-20% within a 194% fractional bandwidth from 0.1 to 6.5 GHz. It also demonstrates better than 11-dB input return loss (RL) and better than 5.1-dB output RL. This PA occupies a chip size of 0.64 mm 2 including pads.