Non-destructive prognosis method of oxide degradation: a rapid monitoring of oxide energy band changes caused by semiconductor processing

A new CMOS transistor and capacitor test structure (Spider's SPIDER), which closely simulates actual IC interconnections, shows that the conductor lines (antennas) connected to the source, drain, and substrate affect the MOS gate damage magnitude significantly. This suggests that to have effective control over plasma charge damage in advanced semiconductor manufacturing, the antenna must be connected to the MOS transistor gate, and the interactions of the antennas connected to the source, drain, and substrate with the gate antenna must be considered. Depending on the relative direction, distance, and size of the antennas connected to the gate, source, drain, and substrate, the magnitude of the charge damage effects can be enhanced or exacerbated. Furthermore, to predict and automatically warn about the potential charge damage in the IC layout design phase, a new charge antenna DRC (design rule check) software has been developed to perform systematic layout checking for the interactions of the ULSI interconnection lines, which become antennas connected to all four terminals of MOS transistors.