Performance comparison of differential static CMOS circuit topologies in SOI technology

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a...

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Bibliographische Detailangaben

Hauptverfasser:	Tretz, C., Chuang, C.T., Terman, L., Pelella, M., Zukowski, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arithmetic Circuit topology Circuits and systems CMOS logic circuits Immune system Logic devices Rails Switches Switching circuits Transconductance
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