Performance comparison of differential static CMOS circuit topologies in SOI technology

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about 2.2 times that of a partially-depleted device at the same bias. We compared three differential static CMOS topologies: (a) standard CMOS logic; (b) push-pull cascode logic (PPCL), a low power high speed static logic topology; (c) complementary pass-transistor logic (CPL), known for its efficiency for device use and popular for fast arithmetic operations. We considered three cases: (a) partially-depleted device with standard bulk-like connection where the body is tied to the supply rail; (b) partially-depleted device with floating body (FB); (c) dual gate (DG) device where the bottom gate is driven with the top gate simultaneously. Based on a methodology described previously (Tretz et al. Proc. IEEE Midwest Symp. on Circuits and Systems, pp. 179-82, 1996), performance comparison of these topologies is sufficient to establish the relative performance of almost any other differential static CMOS topology, using the generic differential CMOS static gate concept. All differential static circuits can be described as a variation of the generic differential static gate comprised of pull-up and pull-down switches, cross-coupled elements, additional resistive loads, and active paths to V/sub dd//GND.