VHDL models for high level synthesis of fuzzy logic controllers

This paper defines a set of the architectural models for implementation of fuzzy logic controllers (FLC) in hardware. These models are defined in order to generate different implementations of FLC. Thus a rapid prototyping is carried out by the generation of the VHDL description of fuzzy systems for simulation and synthesis purpose. The model configuration process can be guided by the specification constraints. Therefore a fuzzy system can be easily and quickly implemented as an application specific integrated circuit (ASIC). In this paper, the synthesis results of some FLC benchmarks using the introduced models are shown.