Sequoia: A High-Endurance NVM-Based Cache Architecture

Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 10 9 -10 12 writes per cell, making a nonvolatile cache (NV-cache) with a lifetime o...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2016-03, Vol.24 (3), p.954-967
Hauptverfasser:	Jokar, Mohammad Reza, Arjomand, Mohammad, Sarbazi-Azad, Hamid
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer architecture Durability Indexes Integrated circuits Interference Lifetime Magnetic tunneling Microprocessors Nonuniformity nonvolatile cache (NV-cache) Nonvolatile memory Proposals Radiation detectors Random access memory Very large scale integration wear-leveling Workload write endurance
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