Sequoia: A High-Endurance NVM-Based Cache Architecture
Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 10 9 -10 12 writes per cell, making a nonvolatile cache (NV-cache) with a lifetime o...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2016-03, Vol.24 (3), p.954-967 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Jokar, Mohammad Reza Arjomand, Mohammad Sarbazi-Azad, Hamid |
| description | Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 10 9 -10 12 writes per cell, making a nonvolatile cache (NV-cache) with a lifetime of dozens of years under ideal working conditions. However, nonuniformity in writes to different cache lines considerably reduces the NV-cache lifetime to a few months. Writes to cache lines can be made uniformly by wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with negligible performance overhead of |
| doi_str_mv | 10.1109/TVLSI.2015.2420954 |
| format | Article |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.954-967 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Computer architecture Durability Indexes Integrated circuits Interference Lifetime Magnetic tunneling Microprocessors Nonuniformity nonvolatile cache (NV-cache) Nonvolatile memory Proposals Radiation detectors Random access memory Very large scale integration wear-leveling Workload write endurance |
| title | Sequoia: A High-Endurance NVM-Based Cache Architecture |
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