Hardware Accelerator for Probabilistic Inference in 65-nm CMOS

A hardware accelerator is presented to compute the probabilistic inference for a Bayesian network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5 V, while achieving a maximum clock frequency of 33 MHz. Clique-tree messag...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2016-03, Vol.24 (3), p.837-845
Hauptverfasser:	Khan, Osama U., Wentzloff, David D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Accelerator boards Accelerators Alarm systems Algorithms Bayes methods Bayesian analysis Bayesian network (BN) clique-tree Consumption embedded machine learning Hardware hardware accelerator Indexes Inference algorithms intelligent sensor node Message passing probabilistic graphical model Probabilistic inference Probabilistic logic Registers Very large scale integration
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