Hardware Accelerator for Probabilistic Inference in 65-nm CMOS
A hardware accelerator is presented to compute the probabilistic inference for a Bayesian network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5 V, while achieving a maximum clock frequency of 33 MHz. Clique-tree messag...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2016-03, Vol.24 (3), p.837-845 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Khan, Osama U. Wentzloff, David D. |
| description | A hardware accelerator is presented to compute the probabilistic inference for a Bayesian network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5 V, while achieving a maximum clock frequency of 33 MHz. Clique-tree message passing algorithm is leveraged to compute the probabilistic inference. The theoretical maximum size of a factor that the proposed hardware accelerator can handle is 2 (8×20) =160 entries, which is sufficient for handling massive BNs, such as PATHFINDER, MUNIN, and so on (>1000 nodes). A Logical Alarm Reduction Mechanism (ALARM) BN is used to benchmark the performance of the accelerator. The accelerator consumes 76 nJ to execute the ALARM network using a clique-tree message-passing algorithm, while the same algorithm executed on an ultralow-power microcontroller consumes 20 mJ. |
| doi_str_mv | 10.1109/TVLSI.2015.2420663 |
| format | Article |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.837-845 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Accelerator boards Accelerators Alarm systems Algorithms Bayes methods Bayesian analysis Bayesian network (BN) clique-tree Consumption embedded machine learning Hardware hardware accelerator Indexes Inference algorithms intelligent sensor node Message passing probabilistic graphical model Probabilistic inference Probabilistic logic Registers Very large scale integration |
| title | Hardware Accelerator for Probabilistic Inference in 65-nm CMOS |
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