CMOS Device Performance Improvement Using Flood Buried-Contact Plasma Doping Processes

An additional ultrashallow boron-based plasma doping (PLAD) was carried out into the source/drain contacts for both pMOS and nMOS devices without masks. The PLAD using either B 2 H 6 or BF 3 gas in a mild energy to ultralow energy (ULE) regime, which are roughly equivalent to 1.5-0.2-keV energy and 1-3 × 10 16 /cm 2 dose regime beam-line B implants, were utilized for this process. The pMOS devices exhibit significant performance improvements, including ~80% lower contact resistances, similar threshold and subthreshold voltage characteristics, and ~15%-30% higher drive currents, without degrading OFF current. Using ULE BF 3 PLAD, the nMOS devices also show performance improvements, including ~50% lower contact resistances, similar threshold and subthreshold voltage characteristics, and ~4% higher drive currents without degrading OFF current. The mechanism of the nMOS device performance improvement can be attributed to the Schottky barrier height lowering effect and deactivation improvement. It significantly reduces cost because this one low-cost PLAD module eliminates two photo steps, one implant step, and two photo removing/cleaning steps.