A High-Speed CMOS Integrated Optical Receiver With an Under-Damped TIA

We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 2 7 -1 PRBS operation with the bit-error rate less than 10 -12 at the incident optical power of -6 and -2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of -.13.7 mW with 1.2 V supply voltage.