Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture

CMOS image sensors are very suitable for battery-operated camera systems due to their low power nature. In this research work, a salient integration mode CMOS image sensor pixel design which requires only 1 or 2 transistors per pixel and a low power readout architecture was developed in a 0.35 µm CMOS technology. High fill factor and small pixel size are achieved at the same time for the 2T pixel design. The readout architecture includes a low voltage low power multi-stage analog data buffer which works as a differential to single-ended conversion mechanism for a new correlated double sampling method. Total data bandwidth and switching power are also greatly reduced. The architecture was developed to be scalable to 0.18 µm technology with 1.2 volt supply voltage, and lower. An experimental chip in an array size of 256 × 256 with a pixel size of 6.3 µm × 6.3 µm was fabricated at a HP's 0.35 µm CMOS technology. Promising experimental results strongly indicates that the new pixel design and readout architecture are suitable for low voltage CMOS camera chips in future generations of CMOS technology.