Optimizing circuits with confidence probability using probabilistic retiming

VLSI circuit manufacturing results in theoretically identical components that actually have varying propagation delays. A "worst-case" or even "average-case" estimation of such delays during the design procedure may be overly pessimistic and will lead to costly and unnecessary redesign cycles. This paper presents a new optimization methodology, called probabilistic retiming, which transforms a circuit based on statistical timing data gathered either from component production histories or from a simulation of the fabrication process. Such circuits are modeled as graphs where each vertex represents a combinational element that has a probabilistic timing characteristic. A polynomial-time algorithm, applicable to such a graph, is developed which retimes a circuit in order to produce a design operating in a specified cycle time within a given confidence level. Experiments show that probabilistic retiming consistently produces faster circuits for a given confidence level, as compared with the traditional retiming algorithm.