A manufacturable embedded fluorinated SiO/sub 2/ for advanced 0.25 /spl mu/m CMOS VLSI multilevel interconnect applications

We have integrated fluorinated SiO/sub 2/ (F-SiO/sub 2/) films with k=3.5 deposited using HDP-CVD into a 0.25 /spl mu/m CMOS process. The significance of this process is that the deposition tool (HDP-CVD) and the processing step (gap fill) are identical to the reference process. We simply replace deposition of undoped SiO/sub 2/ (k=4.0) in HDP-CVD for gap fill with deposition of F-SiO/sub 2/. We have optimized the HDP-CVD process for stable F-SiO/sub 2/ films. The interlevel dielectric (ILD) is composed of HDP-CVD oxide for gap fill and PETEOS for capping before CMP planarization. This ILD structure uses F-SiO/sub 2/ embedded between metal lines. We have compared electrical results obtained from wafers processed using three-level metal 0.25 /spl mu/m CMOS technology with embedded F-SiO/sub 2/ ILD. Results obtained from contact resistance, contact yields and CMOS transistor characteristics are comparable. Moreover, FN stress results show that the gate oxide of NMOS devices has less damage for the F-SiO/sub 2/ split. We have obtained 11% capacitance reduction when comparing embedded F-SiO/sub 2/ to SiO/sub 2/ using metal comb capacitors. The effectiveness of this low k material in circuit performance is also demonstrated. Without optimizing the layout to maximize the benefits of using low k dielectrics in interconnects, the propagation delay of an 88-stage gate array shows 2.5% improvement using embedded F-SiO/sub 2/ as ILD.