A High-Speed FPGA Implementation of an RSD-Based ECC Processor
In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore,...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2016-01, Vol.24 (1), p.151-164 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array. |
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ISSN: | 1063-8210 1557-9999 |
DOI: | 10.1109/TVLSI.2015.2391274 |