A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The...

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Veröffentlicht in:IEEE journal of solid-state circuits 2015-01, Vol.50 (1), p.92-101
Hauptverfasser: Igarashi, Mitsuhiko, Uemura, Toshifumi, Mori, Ryo, Kishibe, Hiroshi, Nagayama, Midori, Taniguchi, Masaaki, Wakahara, Kohei, Saito, Toshiharu, Fujigaya, Masaki, Fukuoka, Kazuki, Nii, Koji, Kataoka, Takeshi, Hattori, Toshihiro
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Sprache:eng
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Zusammenfassung:This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2014.2347353