PTC-Based Sigma-Delta ADCs for High-Speed, Low-Noise Imagers

This letter presents a novel column-parallel readout circuit for image sensors based on incremental-sigma-delta (ISD) ADCs. The excessive number of clock cycles needed per conversion is addressed. We apply the photon transfer curve-based conversion to a second-order ISD ADC, achieving a \(2.75\times \) clock cycles reduction when compared with a standard second-order ISD ADC while maintaining a similar noise performance. This results in the reduction of the pixel readout time and of the size of the digital filter.