Sphinx1: Spectrometric photon counting and integration pixel for X-ray imaging with a 100 electron LSB

Sphinx1 is a novel pixel architecture adapted for X-ray imaging that can detect radiation by photon counting and by charge integration. In photon counting mode, each photon is compensated by one or more counter-charge packets which can be dimensioned at a level as low as 100 electrons and the number...

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Bibliographische Detailangaben
Hauptverfasser: Habib, Amr, Arques, Marc, Dupont, Bertrand, Rohr, Pierre, Sicard, Gilles, Tchagaspanian, Michael, Verger, Loick
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:Sphinx1 is a novel pixel architecture adapted for X-ray imaging that can detect radiation by photon counting and by charge integration. In photon counting mode, each photon is compensated by one or more counter-charge packets which can be dimensioned at a level as low as 100 electrons and the number of injected counter-charge packets indicates the incoming photon energy, thus allowing a spectrometric detection. The pixel is also able to detect radiation by integrating the charges deposited by all incoming photons and converting this analog value into a digital data with a least significant bit (LSB) of 100 electrons through the use of the counter-charge concept. In this paper, Sphinx1 pixel architecture is presented with emphasis on the counter-charge design, and the two modes of operation are described in detail. The pixel was simulated using Eldo simulator. Simulation results indicate an equivalent noise charge (ENC) of 48 electrons-rms for a detector capacitance of 75 fF. The LSB linearity and the ENC are further studied for different values of detector capacitances. The analog and digital power consumptions are calculated to be less than 1μW in static conditions, proving the architecture to be suitable for large area detectors. Finally, corner simulations show a consistent performance against transistors mismatch. Proof of concept test chip of 5 mm × 5 mm test chip is being designed fabricated in CMOS 0.13 μm technology, with a pixel pitch of 200 μm.
ISSN:1082-3654
2577-0829
DOI:10.1109/NSSMIC.2013.6829061