Modeling the power rails in leading edge microprocessor packages

This paper discusses an electrical modeling methodology developed to deal with package power rail (supply) issues for high performance microprocessors. The basic approach is to create a SPICE model of the microprocessor package and IC power rails that mimics the actual physical structures. Grid array style packages with flip mounted dice conveniently partition into two dimensional arrays (planes) interconnected in the third dimension by flip chip bumps, package vias, pins, etc. The key issues are how to partition the system for modeling, how to create the model elements, and how to manage the integration of the model elements. Partitioning is done by choosing a two-dimensional "cell" dimension that provides both acceptable resolution and model complexity. Practical guidelines for creating model subcircuits are discussed. Simulation results representative of a leading edge microprocessor package are presented.