F6: Energy-efficient I/O design for next-generation systems

System power consumption will drive the architecture of future computing systems. From cloud-connected smart phones to the first exaFLOP supercomputers, systems that are the best at managing and minimizing power consumption will hold a key competitive advantage. At the same time, wireline communication bandwidth requirements within these systems will continue to grow exponentially, driving per-lane data rates beyond 25Gb/s and aggregate bandwidth past 1Tb/s while demanding dramatically improved energy efficiency. The objective of this Forum is to provide an overview of ultra-efficient parallel and serial interfaces, advanced memory applications, dense and high-speed optical communication, and platform-driven wired I/O for mobile. The Forum begins with two talks describing how innovative packaging and form factors along with co-design of I/O circuits and interconnects can improve the power/performance tradeoff by more than an order of magnitude. The next two talks address how memory I/O is adapting to meet the aggressive bandwidth and power requirements for systems ranging from cell phones to supercomputers. The next talk explores how to design serial I/O specifically for mobile products, including low-power equalization and clocking and low-latency standby states. The following talk also focuses on energy-efficient clocking and equalization, but explores analog and digital design options for very high-speed link standards. The final two talks highlight recent advances in both discrete and integrated optical transceivers and the power, performance, density and cost benefits for optical in high-performance computing systems.