19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology

19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology

This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-...

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Hauptverfasser: Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim, Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pilseon Yoo, Youngdon Jung, Jinwoo Lee, Jaehyeon Shin, Taeyun Kim, Kunwoo Park, Jinwoong Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer architecture
Couplings
Flash memories
Integrated circuit interconnections
Microprocessors
Noise
Sensors
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Beschreibung
Zusammenfassung:This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-correction coding (ECC), totaling 4MB of capacity. The chip supports negative-level wordline drivability to increase cell Vth margin.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2014.6757455