2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS integrated circuits Optical signal processing Phase locked loops Power transmission lines Synchronization Transmitters
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!