2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s...

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Bibliographische Detailangaben
Hauptverfasser: Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS integrated circuits
Optical signal processing
Phase locked loops
Power transmission lines
Synchronization
Transmitters
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Beschreibung
Zusammenfassung:Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2014.6757329