2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28...

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Hauptverfasser:	Kimura, Hiroshi, Aziz, Pervez, Tai Jing, Sinha, Ashutosh, Narayan, Ram, Hairong Gao, Ping Jing, Hom, Gary, Liang, Anshi, Zhang, Eric, Kadkol, Aniket, Kothari, Ruchi, Chan, Gordon, Yehui Sun, Ge, Benjamin, Zeng, Jason, Ling, Kathy, Wang, Michael, Malipatil, Amaresh, Kotagiri, Shiva, Lijun Li, Abel, Chris, Zhong, Freeman
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Active inductors Clocks Decision feedback equalizers Latches Power demand Transceivers
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