Low Voltage Power Efficient Tunable Shaper Circuit With Rail-To-Rail Output Range for the HYDE Detector at FAIR

This paper presents a low voltage, low power readout front-end system implemented in 130 nm CMOS technology. A conventional architecture that consists of charge sensitive amplifier, pole/zero cancellation and shaper has been used. The work focuses on the design of novel circuit topologies in low voltage environment minimizing the power consumption in modern deep submicron CMOS technologies. An operational amplifier with rail-to-rail output swing that uses a gain boosting technique and class-AB output stage without extra power consumption has been used for the shaper. The circuit combines excellent performances with simplicity of design and suitability for low voltage operation. The system is intended to work with silicon detectors for nuclear physics applications and is optimized to match an input capacitance of 10 pF. The system features a peaking time of 500 ns, a power dissipation of 1.57 mW/channel and an equivalent noise charge of 201 e - .