A 2.6 GB/s multi-purpose chip-to-chip interface

A high-speed interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O interface. Data from the high speed interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.