Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an e...

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Bibliographische Detailangaben
Hauptverfasser: Morooka, Y., Nakase, Y., Choi, J.-M., Shin, H.J., Perlman, D.J., Kolor, D.J., Yoshimura, T., Watanabe, N., Matsuda, Y., Kumanoya, M., Yamada, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Calibration
Circuit testing
Clocks
Delay
Emulation
Packaging
Pins
Synchronization
Timing
Topology
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Beschreibung
Zusammenfassung:SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1998.672416