Effective 3DIC chip module warpage with UF design by analytical method

Three dimensional (3D) stacking technologies have been popular among in high level package that can meet miniaturization trend, high performance, and multi-function electronic products. The interposer where the chips are stacked on is an electrical interface routing between one socket or connection to another. Underfill (UF) material is required to fill in the gap between chip and interposer for protecting u-bumps interconnection. Nevertheless, higher coefficient of thermal expansion (CTE) of UF material to lead chip module of 3DIC package warping, so that to cause bridge or non-wet issue during chip module on substrate process. The purpose of this paper is to study the root cause which influences the warpage of 3D stacked chip module. Firstly, the key factors of underfill material properties were selected by experimental study. Furthermore, The JMP Taguchi Orthogonal Table (L9:3^4) & FEM simulation were implemented to get maximize desirability of UF material property in warpage result of chip module. Finally it is concluded that the final warpage results can be successfully predicted to avoid bridge or non-wet issue during chip module on substrate process.