Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs

Thermal management in 3D ICs not only requires cooling, but may also require thermal isolation in scenarios in which high-power chips (e.g. logic chips) are stacked along with low-power and temperature-sensitive tiers (e.g. memory or silicon nanophotonic chips). A hybrid thermal solution combining within-tier microfluidic cooling for the high-power tier and within-tier thermal isolation for the low-power tier is proposed for the first time. In this paper, we report 1) within-tier microfluidic cooling in a processor-on-processor stack 2) TSVs with 23:1 aspect ratio integrated in the microfluidic heat sink, and 3) the integration of air/vacuum cavity in the low-power tier to `protect' it from the temperature variation and nonuniformity of the high-power chip. Thermal modeling shows that the low-power tier temperature only increases by 4 °C when the power density of the processor tier increases from 50 W/cm 2 to 100 W/cm 2 , compared to 22 °C temperature increase without thermal isolation.