0.35μm, 30V fully isolated and low-Ron nLDMOS for DC-DC applications

In this paper, we present a new approach to integrate in a 0.35 μm BCD technology, low Ron LDMOS power transistors with highly competitive Specific Resistance figure of merit (Rsp, defined as Ron*Area). The LDMOS are fully isolated in order to support applications which may bias the source/drain electrodes below the substrate potential, which is critical for devices used in high-current, high-frequency switching applications. The new devices are suitable for high-efficiency DC-DC converter products with operating voltage of up to 30V, such as mobile PMICs. For maximum performance, two different extended-drain LDMOS structures have been developed to cover the entire operating voltage range: for 16V and below, a planar-gate structure is used and for 20V and above, a non-planar "offset-LOCOS" gate is used for 20V and above.