GrainFlow: Enable data plane innovation at per-bit level

Data plane programmability is regarded as an essential feature of future Internet. However, the flexibility of programmability has not been carefully considered. We present GrainFlow, a hardware-based packet processing platform supporting customization on every header bit's processing and adapting to packet header length variation. We evaluate GrainFlow on a Virtex-5 FPGA board. Experiment results show that users can flexibly redefine the data plane with only 10-20 rules and data plane forwarding rate can achieve wire-speed with acceptable latency increase.