Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are obtained with 81 and -114 mV/nm for n- and p-FETs, respectively. It could be served as an important enhancement tuning factor for threshold voltage (Vth) adjustment in CMOSFETs due to contributions of TaN on Vth values are in the same direction. With CMOS technology moving to below 22-nm node, it is crucial to control amount of wet etch of TaN layer, otherwise device characteristics would be impacted and double hump happens.