Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint
There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mappi...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2013-11, Vol.32 (11), p.1748-1761 |
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container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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creator | Jinho Lee Moo-Kyoung Chung Yeon-Gon Cho Soojung Ryu Jung Ho Ahn Kiyoung Choi |
description | There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mapping and scheduling of tasks and communications on a many-core SoC. The key idea is to decide the type of each communication between message passing and shared memory when we do the mapping and scheduling. By assigning a proper type to each communication, we can optimize the energy consumption, performance, or energy-delay product. To solve the optimization problem, the approach adopts a probabilistic algorithm coupled with some heuristics. To enhance throughput of the system, it performs software pipelined scheduling of the tasks using a modified iterative modulo scheduling technique. Experiments show that our algorithm achieves on average 50.1% lower energy consumption, 21.0% higher throughput, and 64.9% lower energy- delay product, compared to shared memory only communication. |
doi_str_mv | 10.1109/TCAD.2013.2266405 |
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fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_6634549</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6634549</ieee_id><sourcerecordid>10_1109_TCAD_2013_2266405</sourcerecordid><originalsourceid>FETCH-LOGICAL-c265t-bcc21a0e69bff64ee14e5ae8d36383bcdf2ba5e6bb9c43920464f6c1d13475883</originalsourceid><addsrcrecordid>eNo9kMtOwzAQRS0EEqXwAYiNfyDF41eSZRWeUisWbdeR44wh0NiVnS769zS0YjW6o3vu4hByD2wGwMrHdTV_mnEGYsa51pKpCzKBUuSZBAWXZMJ4XmSM5eya3KT0zRhIxcsJMUuz23X-kxrf0pX9wna_HWNwdG3ST_r7V6Hv976zZuiCTzR4ujT-kFUhIl2Fim58i5EugjVbusQ-xMMR8WmIpvPDLblyZpvw7nynZPPyvK7essXH63s1X2SWazVkjbUcDENdNs5piQgSlcGiFVoUorGt441RqJumtFKUnEktnbbQgpC5KgoxJXDatTGkFNHVu9j1Jh5qYPXoqB4d1aOj-uzoyDycmA4R__taC6lkKX4BDYBjdw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint</title><source>IEEE Electronic Library (IEL)</source><creator>Jinho Lee ; Moo-Kyoung Chung ; Yeon-Gon Cho ; Soojung Ryu ; Jung Ho Ahn ; Kiyoung Choi</creator><creatorcontrib>Jinho Lee ; Moo-Kyoung Chung ; Yeon-Gon Cho ; Soojung Ryu ; Jung Ho Ahn ; Kiyoung Choi</creatorcontrib><description>There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mapping and scheduling of tasks and communications on a many-core SoC. The key idea is to decide the type of each communication between message passing and shared memory when we do the mapping and scheduling. By assigning a proper type to each communication, we can optimize the energy consumption, performance, or energy-delay product. To solve the optimization problem, the approach adopts a probabilistic algorithm coupled with some heuristics. To enhance throughput of the system, it performs software pipelined scheduling of the tasks using a modified iterative modulo scheduling technique. Experiments show that our algorithm achieves on average 50.1% lower energy consumption, 21.0% higher throughput, and 64.9% lower energy- delay product, compared to shared memory only communication.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2013.2266405</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Energy consumption ; Many-core ; mapping ; memory constraint ; Memory management ; Message passing ; network-on-chip ; Processor scheduling ; Scheduling ; System-on-chip</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2013-11, Vol.32 (11), p.1748-1761</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c265t-bcc21a0e69bff64ee14e5ae8d36383bcdf2ba5e6bb9c43920464f6c1d13475883</citedby><cites>FETCH-LOGICAL-c265t-bcc21a0e69bff64ee14e5ae8d36383bcdf2ba5e6bb9c43920464f6c1d13475883</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6634549$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6634549$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jinho Lee</creatorcontrib><creatorcontrib>Moo-Kyoung Chung</creatorcontrib><creatorcontrib>Yeon-Gon Cho</creatorcontrib><creatorcontrib>Soojung Ryu</creatorcontrib><creatorcontrib>Jung Ho Ahn</creatorcontrib><creatorcontrib>Kiyoung Choi</creatorcontrib><title>Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mapping and scheduling of tasks and communications on a many-core SoC. The key idea is to decide the type of each communication between message passing and shared memory when we do the mapping and scheduling. By assigning a proper type to each communication, we can optimize the energy consumption, performance, or energy-delay product. To solve the optimization problem, the approach adopts a probabilistic algorithm coupled with some heuristics. To enhance throughput of the system, it performs software pipelined scheduling of the tasks using a modified iterative modulo scheduling technique. Experiments show that our algorithm achieves on average 50.1% lower energy consumption, 21.0% higher throughput, and 64.9% lower energy- delay product, compared to shared memory only communication.</description><subject>Energy consumption</subject><subject>Many-core</subject><subject>mapping</subject><subject>memory constraint</subject><subject>Memory management</subject><subject>Message passing</subject><subject>network-on-chip</subject><subject>Processor scheduling</subject><subject>Scheduling</subject><subject>System-on-chip</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwAYiNfyDF41eSZRWeUisWbdeR44wh0NiVnS769zS0YjW6o3vu4hByD2wGwMrHdTV_mnEGYsa51pKpCzKBUuSZBAWXZMJ4XmSM5eya3KT0zRhIxcsJMUuz23X-kxrf0pX9wna_HWNwdG3ST_r7V6Hv976zZuiCTzR4ujT-kFUhIl2Fim58i5EugjVbusQ-xMMR8WmIpvPDLblyZpvw7nynZPPyvK7essXH63s1X2SWazVkjbUcDENdNs5piQgSlcGiFVoUorGt441RqJumtFKUnEktnbbQgpC5KgoxJXDatTGkFNHVu9j1Jh5qYPXoqB4d1aOj-uzoyDycmA4R__taC6lkKX4BDYBjdw</recordid><startdate>20131101</startdate><enddate>20131101</enddate><creator>Jinho Lee</creator><creator>Moo-Kyoung Chung</creator><creator>Yeon-Gon Cho</creator><creator>Soojung Ryu</creator><creator>Jung Ho Ahn</creator><creator>Kiyoung Choi</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20131101</creationdate><title>Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint</title><author>Jinho Lee ; Moo-Kyoung Chung ; Yeon-Gon Cho ; Soojung Ryu ; Jung Ho Ahn ; Kiyoung Choi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c265t-bcc21a0e69bff64ee14e5ae8d36383bcdf2ba5e6bb9c43920464f6c1d13475883</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Energy consumption</topic><topic>Many-core</topic><topic>mapping</topic><topic>memory constraint</topic><topic>Memory management</topic><topic>Message passing</topic><topic>network-on-chip</topic><topic>Processor scheduling</topic><topic>Scheduling</topic><topic>System-on-chip</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jinho Lee</creatorcontrib><creatorcontrib>Moo-Kyoung Chung</creatorcontrib><creatorcontrib>Yeon-Gon Cho</creatorcontrib><creatorcontrib>Soojung Ryu</creatorcontrib><creatorcontrib>Jung Ho Ahn</creatorcontrib><creatorcontrib>Kiyoung Choi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jinho Lee</au><au>Moo-Kyoung Chung</au><au>Yeon-Gon Cho</au><au>Soojung Ryu</au><au>Jung Ho Ahn</au><au>Kiyoung Choi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2013-11-01</date><risdate>2013</risdate><volume>32</volume><issue>11</issue><spage>1748</spage><epage>1761</epage><pages>1748-1761</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mapping and scheduling of tasks and communications on a many-core SoC. The key idea is to decide the type of each communication between message passing and shared memory when we do the mapping and scheduling. By assigning a proper type to each communication, we can optimize the energy consumption, performance, or energy-delay product. To solve the optimization problem, the approach adopts a probabilistic algorithm coupled with some heuristics. To enhance throughput of the system, it performs software pipelined scheduling of the tasks using a modified iterative modulo scheduling technique. Experiments show that our algorithm achieves on average 50.1% lower energy consumption, 21.0% higher throughput, and 64.9% lower energy- delay product, compared to shared memory only communication.</abstract><pub>IEEE</pub><doi>10.1109/TCAD.2013.2266405</doi><tpages>14</tpages></addata></record> |
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subjects | Energy consumption Many-core mapping memory constraint Memory management Message passing network-on-chip Processor scheduling Scheduling System-on-chip |
title | Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint |
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