Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology
TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub D...
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| Veröffentlicht in: | IEEE transactions on electron devices 1998-04, Vol.45 (4), p.991-993 |
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| container_end_page | 993 |
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| container_issue | 4 |
| container_start_page | 991 |
| container_title | IEEE transactions on electron devices |
| container_volume | 45 |
| creator | Vuong, H.-H. Eshraghi, S.A. Rafferty, C.S. Hillenius, S.J. Pinto, M.R. Diodato, P.W. Cong, H.-I. Zeitzoff, P.M. |
| description | TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub DD/>1.4 V, and for NOR gates with V/sub DD/>2.4 V. |
| doi_str_mv | 10.1109/16.662818 |
| format | Article |
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With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub DD/>1.4 V, and for NOR gates with V/sub DD/>2.4 V.</abstract><pub>IEEE</pub><doi>10.1109/16.662818</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1998-04, Vol.45 (4), p.991-993 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_ieee_primary_662818 |
| source | IEEE Electronic Library (IEL) |
| subjects | Circuit optimization CMOS technology Delay Design optimization Implants Inverters Manufacturing processes Semiconductor device modeling Switches Threshold voltage |
| title | Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology |
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