Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology

Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology

TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub D...

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Veröffentlicht in:IEEE transactions on electron devices 1998-04, Vol.45 (4), p.991-993
Hauptverfasser: Vuong, H.-H., Eshraghi, S.A., Rafferty, C.S., Hillenius, S.J., Pinto, M.R., Diodato, P.W., Cong, H.-I., Zeitzoff, P.M.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit optimization
CMOS technology
Delay
Design optimization
Implants
Inverters
Manufacturing processes
Semiconductor device modeling
Switches
Threshold voltage
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Beschreibung
Zusammenfassung:TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub DD/>1.4 V, and for NOR gates with V/sub DD/>2.4 V.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.662818