Optimized architecture of high order CIC filters

The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher wor...

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Bibliographische Detailangaben
Hauptverfasser:	Pristach, Marian, Pavlik, Michal, Haze, Jiri, Fujcik, Lukas
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits application specific integration circuits cascaded integrator-comb filters Clocks Computer architecture Field programmable gate arrays hardware description language Hogenauer filter Interpolation Power demand Software
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Beschreibung
Zusammenfassung:	The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.