Implementing fair queueing in ATM switches: the discrete-rate approach

The total implementation cost of schedulers which approximate the generalized processor sharing (GPS) policy is dominated by the complexity of maintaining and sorting the time-stamps for all connections. Several approaches have been proposed which reduce the cost of the sorting operation and only introduce a small degradation in the delay bounds of the scheduler; they include logarithmic calendar queues and schedulers supporting a discrete set of guaranteed rates. All these techniques still require computing and storing one time-stamp per connection, thus maintaining the cost of GPS-related algorithms clearly higher than that of less sophisticated schedulers. Furthermore, in the case of the discrete-rate approach, the complexity increases linearly with the number of supported rates, thus making it attractive only for relatively small numbers of rates. In this paper, we introduce a discrete-rate GPS-related scheduler which does not require the computation and storage of one time-stamp per connection, and only maintains a single time-stamp per rate. The elimination of the per-connection time-stamps has no negative effect on the delay bounds. Then, we present a generalized discrete-rate approach, which uses a given number of FIFO queues to support a larger number of guaranteed rates, and only introduces a modest degradation in delay bounds for certain rates. The technique can be applied to our no-per-connection-time-stamp scheduler, as well as to any discrete-rate scheduler.