A new erasing method for a single-voltage long-endurance flash memory

A new method to erase a standard (double-poly, stacked-gate NOR-type) flash cell is proposed. The method, still using the tunneling mechanism to extract electrons from the floating gate, is based on the concept of keeping the electric field constant during the whole erasing operation. The new method...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE electron device letters 1998-02, Vol.19 (2), p.37-39
Hauptverfasser: Bez, R., Cantarelli, D., Moioli, L., Ortolani, G., Servalli, G., Villa, C., Dallabora, M.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A new method to erase a standard (double-poly, stacked-gate NOR-type) flash cell is proposed. The method, still using the tunneling mechanism to extract electrons from the floating gate, is based on the concept of keeping the electric field constant during the whole erasing operation. The new method has two main advantages with respect to the conventional one: (1) it does not depend on the supply voltage variation and (2) it allows a better reliability in terms of endurance-induced stress. Results have shown that flash device performances are greatly improved in terms of stability and endurance reliability up to one million cycles.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.658595