High performance extremely-thin body InAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D by contact resistance reduction technology
In this paper, we presents 20-nm-channel length (L ch ) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (I on ) and maximum transconductance...
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| creator | Kim, S. H. Yokoyama, M. Nakane, R. Ichikawa, O. Osada, T. Hata, M. Takenaka, M. Takagi, S. |
| description | In this paper, we presents 20-nm-channel length (L ch ) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (I on ) and maximum transconductance (G m ) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V D ) of 0.5 V. This high performance is attributable to the low S/D parasitic resistance (R SD ), which was realized by a cleaning process of Ni-InGaAs surfaces before pad electrode deposition as well as increase in indium (In) content in channel layer. Furthermore, it was found that the interface resistance (R interface ) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing In content in the channel layers. |
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H. ; Yokoyama, M. ; Nakane, R. ; Ichikawa, O. ; Osada, T. ; Hata, M. ; Takenaka, M. ; Takagi, S.</creator><creatorcontrib>Kim, S. H. ; Yokoyama, M. ; Nakane, R. ; Ichikawa, O. ; Osada, T. ; Hata, M. ; Takenaka, M. ; Takagi, S.</creatorcontrib><description>In this paper, we presents 20-nm-channel length (L ch ) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (I on ) and maximum transconductance (G m ) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V D ) of 0.5 V. This high performance is attributable to the low S/D parasitic resistance (R SD ), which was realized by a cleaning process of Ni-InGaAs surfaces before pad electrode deposition as well as increase in indium (In) content in channel layer. Furthermore, it was found that the interface resistance (R interface ) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing In content in the channel layers.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 9781467352260</identifier><identifier>ISBN: 1467352268</identifier><identifier>EISBN: 9784863483477</identifier><identifier>EISBN: 4863483473</identifier><language>eng</language><publisher>IEEE</publisher><subject>Aluminum oxide ; Cleaning ; Indium gallium arsenide ; Logic gates ; MOSFET ; Resistance</subject><ispartof>2013 Symposium on VLSI Technology, 2013, p.T52-T53</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6576682$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6576682$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kim, S. 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This high performance is attributable to the low S/D parasitic resistance (R SD ), which was realized by a cleaning process of Ni-InGaAs surfaces before pad electrode deposition as well as increase in indium (In) content in channel layer. Furthermore, it was found that the interface resistance (R interface ) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing In content in the channel layers.</description><subject>Aluminum oxide</subject><subject>Cleaning</subject><subject>Indium gallium arsenide</subject><subject>Logic gates</subject><subject>MOSFET</subject><subject>Resistance</subject><issn>0743-1562</issn><isbn>9781467352260</isbn><isbn>1467352268</isbn><isbn>9784863483477</isbn><isbn>4863483473</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tOAjEARceoiYp8gZv-QGPfjyVBBRKUBexJp9NhamZa0pbo_IGfLUFXN3dxz8m9qqZaKqYEZYoyKa8vHTMhKSdEoJvqHklGIeaC3FUPOX8iRBCn6r76WfpDB44utTENJlgH3HdJbnD9CEvnA6hjM4JVmGUYA_Qhn3pTYgLvm-3b6y6DGMDWgy9fOvDh4SoszCyDwRXTg-3zC6hHYGMoxhaQXPa5XBTJNSdb_HlbnO1C7ONhfKxuW9NnN_3PSbU7C-ZLuN4sVvPZGnqNCiRYciuMFppaTEzNFa8JQq3RGGtCa0u5pg05v8W6kQ12nNcNY5w1VjHTIjqpnv6w3jm3PyY_mDTuBZdCKEJ_AUG8X5M</recordid><startdate>201306</startdate><enddate>201306</enddate><creator>Kim, S. H.</creator><creator>Yokoyama, M.</creator><creator>Nakane, R.</creator><creator>Ichikawa, O.</creator><creator>Osada, T.</creator><creator>Hata, M.</creator><creator>Takenaka, M.</creator><creator>Takagi, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201306</creationdate><title>High performance extremely-thin body InAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D by contact resistance reduction technology</title><author>Kim, S. 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H.</creatorcontrib><creatorcontrib>Yokoyama, M.</creatorcontrib><creatorcontrib>Nakane, R.</creatorcontrib><creatorcontrib>Ichikawa, O.</creatorcontrib><creatorcontrib>Osada, T.</creatorcontrib><creatorcontrib>Hata, M.</creatorcontrib><creatorcontrib>Takenaka, M.</creatorcontrib><creatorcontrib>Takagi, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, S. H.</au><au>Yokoyama, M.</au><au>Nakane, R.</au><au>Ichikawa, O.</au><au>Osada, T.</au><au>Hata, M.</au><au>Takenaka, M.</au><au>Takagi, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High performance extremely-thin body InAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D by contact resistance reduction technology</atitle><btitle>2013 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2013-06</date><risdate>2013</risdate><spage>T52</spage><epage>T53</epage><pages>T52-T53</pages><issn>0743-1562</issn><isbn>9781467352260</isbn><isbn>1467352268</isbn><eisbn>9784863483477</eisbn><eisbn>4863483473</eisbn><abstract>In this paper, we presents 20-nm-channel length (L ch ) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (I on ) and maximum transconductance (G m ) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V D ) of 0.5 V. This high performance is attributable to the low S/D parasitic resistance (R SD ), which was realized by a cleaning process of Ni-InGaAs surfaces before pad electrode deposition as well as increase in indium (In) content in channel layer. Furthermore, it was found that the interface resistance (R interface ) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing In content in the channel layers.</abstract><pub>IEEE</pub></addata></record> |
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| subjects | Aluminum oxide Cleaning Indium gallium arsenide Logic gates MOSFET Resistance |
| title | High performance extremely-thin body InAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D by contact resistance reduction technology |
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