High performance extremely-thin body InAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D by contact resistance reduction technology

In this paper, we presents 20-nm-channel length (L ch ) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (I on ) and maximum transconductance (G m ) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V D ) of 0.5 V. This high performance is attributable to the low S/D parasitic resistance (R SD ), which was realized by a cleaning process of Ni-InGaAs surfaces before pad electrode deposition as well as increase in indium (In) content in channel layer. Furthermore, it was found that the interface resistance (R interface ) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing In content in the channel layers.