A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 2...

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Hauptverfasser: Min-Cheng Chen, Chang-Hsien Lin, Yun-Fang Hou, Yi-Ju Chen, Chia-Yi Lin, Fu-Kuo Hsueh, Hsin-Liang Liu, Cheng-Tsai Liu, Bo-Wei Wang, Hsiu-Chih Chen, Chun-Chi Chen, Shih-Hung Chen, Chien-Ting Wu, Tung-Yen Lai, Mei-Yi Lee, Bo-Wei Wu, Cheng-San Wu, Ivy Yang, Yi-Ping Hsieh, ChiaHua Ho, Tahui Wang, Sachid, Angada B., Chenming Hu, Fu-Liang Yang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
FinFETs
Logic gates
Noise
Silicon
SRAM cells
Very large scale integration
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Zusammenfassung:For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
ISSN:0743-1562