A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

This paper presents a novel 1Mb STT-MRAM for power and area reduction of cache memory in micro-processors. This memory adopts current-integral sensing scheme for high speed read, and uses advanced perpendicular STT-MRAM for high speed write to achieve 250 MHz operation, 17.8 mW read power and 46.5 m...

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Hauptverfasser: Noguchi, Hiroki, Kushida, Keiichi, Ikegami, Kazutaka, Abe, Keiko, Kitagawa, Eiji, Kashiwada, Saori, Kamata, Chikayoshi, Kawasumi, Atsushi, Hara, Hiroyuki, Fujita, Shinobu
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cache memory
Computer architecture
Magnetic tunneling
Microprocessors
Nonvolatile memory
Random access memory
Sensors
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Zusammenfassung:This paper presents a novel 1Mb STT-MRAM for power and area reduction of cache memory in micro-processors. This memory adopts current-integral sensing scheme for high speed read, and uses advanced perpendicular STT-MRAM for high speed write to achieve 250 MHz operation, 17.8 mW read power and 46.5 mW write power per 256-b I/O. Using a processor simulator, it has been confirmed the total cache power is reduced, whereas those for STT-MRAMs previously reported are increased compared with that for SRAM.
ISSN:0743-1562